This invention relates to a method for producing MOS semiconductor devices, and more particularly, to such a method which substantially completely eliminates the incidence of fatal defects in a device as a consequence of defects in, and/or misalignment between, the usual several photolithography masks which heretofore have been used in the production of such devices.
For the purpose of illustration herein, a preferred manner of practicing the invention is described in the context of making field-effect, power-MOS transistors, in the manufacture of which the invention has been found to have particular utility. Application of the invention to the making of other specific MOS semiconductor devices, of course, will be immediately apparent to those skilled in the art.
In the prior art fabrication, on silicon wafers, of transistor devices, such as field-effect, power-MOS transistors, there has been a significant problem in (1) obtaining an acceptably high yield of relatively large-current-capability transistors without (2) driving the cost of production to extremely high and unacceptable levels. A major contributor to this problem in the past has been that the best known prior art fabrication techniques typically employ five or more independent masking, diffusion and metallization steps, with each offering a significant opportunity for the creation of a fatal error in a device. Generally speaking, the more the number of such steps, the greater the possibility for the occurrence of catastrophic defects.
These defects come about primarily because of misalignment occurring during the successive masking steps, and also in situations where one or more of the masks may, individually, have localized defects. Also, there is a possibility of fatal defects occurring as a result of airborne contaminants that may collect on a mask or a wafer, and this possibility, of course, is also aggravated by the plurality of masking steps now required.
As a consequence of this problem, it has not been economically feasible, with any expectation of achieving an acceptably high yield, to manufacture relatively large, high-current-capability devices. Put another way, the larger the design of the device, the greater is the likelihood that it will contain a fatal defect. To date, an economically practical size limit has been about 0.25-inches on each side of a device. Accordingly, the tendency in the past has been to reduce the size of individual devices so that the chance of a larger number of smaller devices surviving defects increases. However, these smaller devices, while emerging with an acceptable yield percentage, are capable only of handling relatively low-level currents, and thus low-power applications. Accordingly, they must be linked electrically in collections in some fashion in order to be able to handle relatively high-power applications.
Efforts in the past to improve the yield of larger-surface-area devices has taken place primarily through directing attention to several matters, key among which are performing the manufacturing steps in the cleanest possible environment, creating masks under extremely expensive manufacturing conditions, and handling mask alignment through very sophisticated, precise alignment machines. These areas of attention are extremely expensive, and, as a practical matter, make their use economically unattractive vis-a-vis the final market price which, as a consequence, must be attached to a finished device.
A general object of the present invention, therefore, is to provide a novel manufacturing procedure which is capable of reducing, substantially to zero, the percentage likelihood that a fatal defect will occur in a final MOS semiconductor device, even though that device may occupy the entire usuable area (i.e. as a single device) on a substrate, such as a silicon wafer.
A related object, accordingly, is to provide such a procedure which offers a simple and very low-cost process enabling the production of high-yield, defect-free MOS semiconductor devices which are capable, as individuals, of handling strikingly larger currents than are now practically handleable.
The key to the simplicity, effectiveness and cost advantage of the invention is that, according to one manner of practicing it, only a single, independent mask is required in the production of the usual plural, functional regions in a semiconductor device, and according to another way of practicing the invention, no mask at all is required. The invention, importantly, through the use of a dopant protective layer which protects an initially established MOS oxide layer, and layer which ultimately disappears, offers excellent and simply effected, control over the doping steps used to create the necessary operative junctions. These statements, essentially, summarize the heart of the invention, whose other objects and advantages will become more fully apparent as the description which now follows is read in conjunction with the drawings.